台积电和Cadence宣布合作，为 AI 驱动的先进节点设计和 3D-IC 提供更强大的支持，以满足日益增长的 AI 应用需求。该合作涵盖了数字和定制设计流程、Cadence.AI 平台、Cadence Integrity 3D-IC 平台以及关键 IP，以优化性能、提高生产力并加速上市时间。

🤝 台積電與 Cadence 合作，針對台積電最新的 N3 和 N2P 製程技術，認證了 Cadence 的業界領先數位和客製化設計流程，以進行實作和簽核。作為長期合作的設計技術共同優化 (DTCO) 夥伴，台積電和 Cadence 持續透過合作優化 A16 的功耗、效能和面積 (PPA)，並新增 EDA 功能以支援反面布線等先進功能。

🤖 Cadence.AI：Cadence 和台積電也在合作 Cadence.AI，以 AI 驅動下一代數位和類比設計自動化，提供業界領先的生產力和結果品質。Cadence.AI 是涵蓋設計和驗證所有方面的晶片到系統 AI 平台。台積電和 Cadence 的合作重點在於三個主要領域： * Cadence Cerebrus 智能晶片探索器將 AI 應用於數位設計，以收斂到最佳的 PPA。 * Cadence Joint Enterprise Data and AI (JedAI) 平台使用生成式 AI 進行設計除錯和分析，協助 PPA 分析。 * Cadence 的 Virtuoso Studio 允許將遺留的客製化和類比設計遷移到現代節點，並執行電路最佳化和高西格瑪蒙地卡羅分析。

📦 Cadence Integrity 3D-IC 平台：Cadence Integrity 3D-IC 平台是領先的系統級探索解決方案，也是單一供應商平台，可統一封裝、類比和數位實作，讓高效的 3D-IC 設計成為可能。這透過支援所有最新的 3Dblox 功能和結構，開闢了創新的新機會。為了支援台積電 3DFabric 技術中的超高密度互連，台積電和 Cadence 正在合作開發下一代高容量基板路由器，用於晶片對晶片和晶片對基板連接。

⚡ 關鍵 IP：AI 工廠對資料的永不滿足的胃口，正在提高對互連的需求，並推動功耗包絡。Cadence 擁有廣泛的關鍵 IP 組合，可有效地在晶片之間以及資料中心之間移動資料，包括 Universal Chiplet Interconnect Express (UCIe) 1.0、PCI Express (PCIe) 6.0，以及世界上第一個在台積電 N3 上以 32Gbps 執行且經過矽驗證的 GDDR7，這為資料中心和網路邊緣的 AI 介面提供了最佳效能。為了解決這些晶片之間日益增長的通訊挑戰，Cadence 矽光子設計支援解決方案支援台積電的 Compact Universal Photonic Engine (COUPE)。

🚗 汽車領域：台積電和 Cadence 正與汽車領域的領導者共同合作。隨著當今汽車設計中的矽含量持續增長，針對當前和未來製程節點（例如台積電 N5A 和後續的 N3A）的 IP 開發變得更加關鍵。

☁️ 雲端設計流程：台積電和 Cadence 也合作展示了 Cadence 前端到後端晶片設計流程在雲端針對台積電的先進製程節點所提供的準確性和可擴展性。透過這項合作，共同客戶可以透過採用 Cadence 的各種雲端解決方案來縮短設計時程。

Highlights:

AI-driven digital and custom design flows available for the latest TSMC N2P and N3 technologies

Cadence is collaborating with TSMC on A16 design solutions to optimize PPA

Cadence Integrity 3D-IC Platform unifying packaging, analog and digital design supports latest 3Dblox features

Collaboration includes Celsius Studio mechanical analysis enablement and thermal/voltage impacts on power/IR/STA and what-if in-design analysis

Design IP powers the AI factory, including the industry’s first silicon-proven GDDR7 IP running at 32Gbps on the TSMC N3 technology

Cadence solutions support secure chip design in the cloud, with design solutions to support TSMC silicon photonics technologies

Cadence Design Systems, Inc., announced that it is collaborating with TSMC to enhance productivity and optimize product performance for AI-driven advanced-node designs and 3D-ICs. The rapid adoption of AI applications has created unprecedented demand for advanced silicon solutions capable of handling colossal datasets and computations. To meet these escalating requirements, the industry is pushing the boundaries of advanced-node silicon and 3D-IC technologies. TSMC and Cadence are at the forefront of this revolution, together empowering customers to accelerate time to market while increasing performance.

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“Together, we are revolutionizing the future of silicon design with AI-powered EDA software, enabled for TSMC’s latest process technologies. Our ongoing collaboration on innovative solutions for next-generation technologies like TSMC A16 and 3Dblox is paving the way for the AI factories of tomorrow.”

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TSMC has certified Cadence’s industry-leading digital and custom design flows for implementation and signoff on TSMC’s latest N3 and N2P process technologies. As long-standing design technology co-optimization (DTCO) partners, TSMC and Cadence continue that tradition by collaborating to optimize power, performance and area (PPA) on A16, adding EDA features to enable advanced features such as backside routing.

Cadence and TSMC are also collaborating on Cadence.AI to drive next-generation digital and analog design automation fueled by AI, delivering industry-leading productivity and quality of results. Cadence.AI is a chips-to-systems AI platform spanning all aspects of design and verification. The collaboration between TSMC and Cadence is focused on three main domains:

The Cadence Cerebrus Intelligent Chip Explorer applies AI to digital design for converging on the optimal PPA.
The Cadence Joint Enterprise Data and AI (JedAI) Platform uses generative AI for design debug and analytics, helping with PPA analysis.
Cadence’s Virtuoso Studio enables migrating legacy custom and analog designs to modern nodes and performs circuit optimization and high-sigma Monte Carlo analysis.
The Cadence Integrity 3D-IC Platform is a leading system-level exploration solution and a single-vendor platform that unifies packaging, analog and digital implementation—making efficient 3D-IC design possible. This opens new opportunities for innovation by supporting all the latest 3Dblox features and constructs. To enable the ultra-high-density interconnect in TSMC 3DFabric technologies, TSMC and Cadence are collaborating on a next-generation high-capacity substrate router for die-to-die and die-to-substrate connections.

Multiphysics analyses and optimization is a critical dimension of success for 3D-IC technologies. TSMC and Cadence are collaborating to enable warpage/stress analysis for TSMC 3DFabric in addition to electrical/thermal analysis, and Cadence’s Celsius™ Studio warpage/stress analysis simulation results have been validated. Thermal and voltage impacts on power/IR/STA are also enabled and verified inside the Cadence Integrity 3D-IC Platform for TSMC 3DFabric.

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The AI factories’ insatiable appetite for data is increasing the requirements for interconnects and pushing power envelopes. Cadence has a broad portfolio of critical IP for efficiently moving data between chiplets and across data centers, including Universal Chiplet Interconnect Express (UCIe) 1.0, PCI Express (PCIe) 6.0 and the world’s first silicon-proven GDDR7 on TSMC N3, running at 32Gbps, which provides the b*********/performance for AI interfaces in both data centers and network edges. To address the growing communication challenges between these chips, Cadence silicon photonics design enablement solutions support TSMC’s Compact Universal Photonic Engine (COUPE).

TSMC and Cadence are jointly collaborating with the leaders in the automotive space. As the silicon content in today’s automotive designs continues to grow, IP development for current and future process nodes, such as TSMC N5A and later N3A, is even more critical.

TSMC and Cadence have also collaborated to showcase the accuracy and scalability offered by Cadence’s front-to-backend chip design flows on the Cloud for TSMC’s advanced process nodes. Through this collaboration, mutual customers can shorten design schedules by adopting Cadence’s wide range of Cloud solutions.

“TSMC and Cadence have a long-standing, successful partnership that turns the world’s designs into silicon reality,” said Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Together, we are revolutionizing the future of silicon design with AI-powered EDA software, enabled for TSMC’s latest process technologies. Our ongoing collaboration on innovative solutions for next-generation technologies like TSMC A16 and 3Dblox is paving the way for the AI factories of tomorrow.”

“In collaboration with Cadence, we’ve successfully enabled AI-optimized design flows for TSMC’s N2 technology and are driving advancements in 3D-IC design,” said Dan Kochpatcharin, head of Ecosystem and Alliance Management Division at TSMC. “This marks a significant leap forward in digital and custom solutions, paving the way for the technology innovations that will power the AI infrastructure.”

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