AiThority 2024年09月09日
Tenstorrent and Movellus Form Strategic Engagement for Next-Generation Chiplet-Based AI and HPC Solutions
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Tenstorrent许可Movellus的数字IP家族,双方合作开发基于芯片let的解决方案,以优化功耗并提升性能。

🎯Movellus的Aeonic Digital IP使Tenstorrent能利用先进时钟技术降低整体能耗,其产品旨在解决现代计算中的关键基础设施挑战,如片上感应、数字时钟和电力输送等。

🎯数字自适应时钟系列促进了架构进步,如每个核心的分布式时钟和细粒度动态频率缩放(DFS)。与下垂探测器结合时,提供先进的时钟管理能力,可在减少Vmin的同时最小化性能影响。

🎯Movellus的数字时钟技术使Tenstorrent能在芯片上分布数字PLLs,提供本地化、细粒度的时钟,其过程无关的数字架构为多种设备提供了统一的软件接口。

Enabling Cross-Foundry IP for Power and Performance Optimization

Movellus and Tenstorrent announced that Tenstorrent has licensed Movellus’ digital IP family as part of a strategic engagement, for its AI and HPC chiplet solutions. This collaboration aims to leverage the strengths of both companies to develop chiplet-based solutions that enhance performance while optimizing power consumption. Movellus Aeonic Digital IP allows Tenstorrent to leverage advanced clocking techniques to reduce overall energy consumption.

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“By collaborating with Movellus and integrating their technology, we are optimizing power efficiency in our processors and continuing to drive Tenstorrent’s leadership in scalable AI chiplets,” said Keith Witek, Chief Operating Officer of Tenstorrent.

Movellus’ Aeonic portfolio offers products designed to tackle critical infrastructure challenges in modern computing, such as on-die sensing, digital clocking, and power delivery. Notably, the digital adaptive clocking family facilitates architectural advancements like per-core distributed clocking and fine-grained dynamic frequency scaling (DFS). Additionally, when coupled with droop detectors, these products provide advanced clock management capabilities, allowing for Vmin reduction by effectively mitigating droop while minimizing any performance impact. With these products it is possible to combine localized clocking, DFS, DVFS, and droop mitigation in a unified solution, simplifying design and easing integration.

“Movellus’ digital clocking technology enables us to distribute digital PLLs across our chip to provide a localized, fine-grained clocking, something that is not possible with traditional analog PLLs,” said Michael Smith, Senior Director of SoC Hardware Engineering at Tenstorrent. “In addition, their process agnostic digital architecture provides a cohesive software interface across multiple devices.”

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“Tenstorrent is pioneering AI and HPC compute with their novel and scalable hardware architectures and software stack,” said Mo Faisal, CEO of Movellus. “We are grateful to be a part of this ground-up approach that is foundational to the advancement of AI and HPC compute with an intention of maximizing energy efficiency – a much-needed development in the age of AI.”

[To share your insights with us as part of editorial or sponsored content, please write to psen@itechseries.com]

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Tenstorrent Movellus 芯片let 能耗优化
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