Heterojunction (HJT) is a prominent high-efficiency cell technology that has evolved into a serious contender for mainstream solar production. Built on the foundation of marrying crystalline silicon with thin-film amorphous silicon layers, it stands out as a unique approach among PV cell technologies that has been particularly attractive to newcomers looking to avoid launching yet another ‘me-too’ product. However, despite its promise, HJT has often remained a contender rather than becoming mainstream, largely due to its higher costs both in terms of CapEx and OpEx. Nevertheless, the technology has secured a loyal group of serious followers who have established multi-gigawatt-scale manufacturing facilities, driven by several undeniable advantages. HJT offers benefits such as low-temperature processing, a reduced number of process steps, high bifaciality, and a superior temperature coefficient. Moreover, it is widely regarded as an ideal platform for the development of future tandem solar cells. Against this backdrop, we summarize a range of important developments in the HJT segment in this chapter.
Like with other commercial advanced cell technologies, HJT also uses n-type base wafers. However, compared to its peer technologies, HJT is most forgiving in terms of wafer quality.
Electrical Parameters
It is already established that in order to address the requirement for high wafer quality, the industry has adopted a heat treatment process (annealing) that mimics gettering, a process of removing metallic impurities with thermal treatment. As a result, HJT can now use wafers from different positions of the ingot and production runs of the crucible. Annealing is now the standard in the HJT process sequence. An important development with respect to wafer requirements for HJT is its compatibility with low-cost wafers originating from the rechargeable Czochralski (CZ) technology. In this method, after the initial silicon melt is depleted during ingot pulling, the crucible is refilled with a new charge of polysilicon, allowing continuous operation.
While the process results in higher oxygen content, this is not a concern for HJT. That’s because HJT does not involve steps involving high temperatures, which would otherwise activate oxygen-related defects. Moreover, it also allows the integration of another low-cost process upstream. The ingot pulling process can also use the low-cost granular silicon produced with the fluidized bed reactor (FBR), which results in slightly lower purity than the standard method, but still aligns well with the requirements for HJT. Wafer producers like LONGi (with its new TaiRay wafer technology) have also raised the bar in overall wafer quality.
The table below lists the typical wafer specs for HJT cells. HJT wafers come in 2 main resistivity ranges: 0.3 - 2.1 Ω·cm and 1–7 Ω·cm, with 0.3 - 2.1 Ω·cm being the mainstream. The minority carrier lifetime of HJT wafers varies significantly depending on resistivity. In general, HJT wafers have lower lifetime requirements compared to TOPCon wafers.
When it comes to physical properties, the majority of HJT producers have adapted to half-wafer processing. This enables them to improve the ingot utilization rate by deriving the half bricks from the slide slabs of the ingot.
An even more compelling topic related to wafers when it comes to HJT is thickness; to be specific, the ability to process thin wafers. Huasun Energy, a leading HJT manufacturer, reported using wafers around 120 µm thick in mid-2024, with a target to reach 110 µm by the end of that year. At the TaiyangNews High Efficiency Solar Technologies Conference held in December 2024, Huasun, as well as Risen, another HJT leader, announced that 100 µm has already entered production, while a thickness of 90 µm is being evaluated. However, companies put an 80 µm cap for wafer thickness reduction, as any further lowering beyond this would start affecting efficiency (see Day 2: TaiyangNews High Efficiency Solar Technologies 2024 Conference).
Both CPIA and ITRPV project a continuous decrease in wafer thickness, although their forecasts differ in specific figures and timelines. According to CPIA, HJT technology has led wafer thickness reduction efforts, reaching 110 µm last year. This is expected to further decrease to 105 µm this year and to 100 µm by 2026, although the pace of reduction is anticipated to slow thereafter, reaching 90 µm by 2030. In comparison, ITRPV projects relatively higher wafer thicknesses. According to ITRPV, wafer thickness is expected to decline from 125 µm last year to below 120 µm this year, eventually reaching 100 µm by 2032.
