本文探讨了将大型语言模型(LLM)应用于硬件设计，特别是VHDL代码解释的实践。尽管Verilog更受欢迎，但VHDL在行业中仍然重要。针对高性能处理器设计的独特需求，本文介绍了如何开发专门用于解释VHDL代码的LLM。通过定制测试集和扩展预训练(EPT)，模型在代码解释方面的专家评估得分从43%提高到69%。此外，还开发了一种LLM作为评估者，用于评估模型。实验结果表明，通过指令调整和使用更新的基础模型，专家评估得分有望达到85%以上。本文最后讨论了如何利用生成式AI领域的最新进展来进一步提高硬件设计LLM的质量。

💡 大语言模型(LLM)在硬件设计中扮演日益重要的角色，尤其是在提高芯片设计师的生产力方面。本文聚焦于LLM在VHDL代码解释中的应用，这在拥有数十年高性能处理器设计经验的组织中尤为重要。

🧪 通过开发针对特定需求的测试集，并对基础LLM进行扩展预训练(EPT)，显著提高了模型解释VHDL代码的准确性。专家评估显示，EPT模型的代码解释质量从43%提升至69%。

⚖️ 创新性地开发了一种LLM作为评估者，用于评估其他模型，其评估结果与专家评估员的判断相近。这为模型迭代和优化提供了更高效的手段。

🚀 实验结果表明，通过对EPT模型进行指令调整，并结合更新的基础模型，代码解释质量有望进一步提升，专家评估得分预计可达到85%甚至更高。

arXiv:2505.09610v1 Announce Type: cross Abstract: The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has been considerable discussion about the use of LLMs in RTL specifications of chip designs, for which the two most popular languages are Verilog and VHDL. LLMs and their use in Verilog design has received significant attention due to the higher popularity of the language, but little attention so far has been given to VHDL despite its continued popularity in the industry. There has also been little discussion about the unique needs of organizations that engage in high-performance processor design, and techniques to deploy AI solutions in these settings. In this paper, we describe our journey in developing a Large Language Model (LLM) specifically for the purpose of explaining VHDL code, a task that has particular importance in an organization with decades of experience and assets in high-performance processor design. We show how we developed test sets specific to our needs and used them for evaluating models as we performed extended pretraining (EPT) of a base LLM. Expert evaluation of the code explanations produced by the EPT model increased to 69% compared to a base model rating of 43%. We further show how we developed an LLM-as-a-judge to gauge models similar to expert evaluators. This led us to deriving and evaluating a host of new models, including an instruction-tuned version of the EPT model with an expected expert evaluator rating of 71%. Our experiments also indicate that with the potential use of newer base models, this rating can be pushed to 85% and beyond. We conclude with a discussion on further improving the quality of hardware design LLMs using exciting new developments in the Generative AI world.